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esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 1/64 ddr ii sdram 8m x 16 bit x 4 banks ddr ii sdram features ? jedec standard ? v dd = 1.8v 0.1v, v ddq = 1.8v 0.1v ? internal pipelined double-data-rate architecture; two data access per clock cycle ? bi-directional differential data strobe (dqs, dqs ); dqs can be disabled for single-ended data strobe operation. ? on-chip dll ? differential clock inputs (clk and clk ) ? dll aligns dq and dqs transition with clk transition ? quad bank operation ? cas latency : 3, 4, 5, 6, 7 ? additive latency: 0, 1, 2, 3, 4, 5, 6 ? burst type : sequential and interleave ? burst length : 4, 8 ? all inputs except data & dm are sampled at the rising edge of the system clock(clk) ? data i/o transitions on both edges of data strobe (dqs) ? dqs is edge-aligned with data for read; center-aligned with data for write ? data mask (dm) for write masking only ? off-chip-driver (ocd) impedance adjustment ? on-die-termination for better signal quality ? special function support - 50/ 75/ 150 ohm odt - high temperature self refresh rate enable - duty cycle corrector - partial array self refresh (pasr) ? auto & self refresh ? refresh cycle : - 8192 cycles/64ms (7.8 s refresh interval) at 0 Q t c Q + 85 - 8192 cycles/32ms (3.9 s refresh interval) at + 85 t c Q +95 ? sstl_18 interface ? if t ck < 1.875ns, the device can not support wr ite with auto precharge function.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 2/64 control logic dm dq mode register & extended mode register column address buffer & refresh counter row address buffer & refresh counter row decoder sense amplifier column decoder data control circuit input & output buffer address clock generator clk clk cke cs ras cas we dll clk, clk odt dqs, dqs ordering information: product id max freq. v dd data rate (cl-trcd-trp) package comments m14d5121632a -1.3bg2k * 750mhz 1.8v ddr2-1500 (7-10-10) m14d5121632a -1.5bg2k 667mhz 1.8v ddr2-1333 (7-9-9) m14d5121632a -1.8bg2k 533mhz 1.8v ddr2-1066 (7-7-7) m14d5121632a -2.5bg2k 400mhz 1.8v ddr2-800 (5-5-5) 84 ball bga a(max) = 1.2mm m14d5121632a -1.8bbg2k 533mhz 1.8v ddr2-1066 (7-7-7) m14d5121632a -2.5bbg2k 400mhz 1.8v ddr2-800 (5-5-5) 84 ball bga a(max) = 1.0mm pb-free note: * all specification for speed grade -1.3 is preliminary data. functional block diagram bank a command decoder bank d latch circuit bank b bank c
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 3/64 ball configuration (top view) (bga84, 8mmx12.5mmx1.2mm body, 0.8mm ball pitch) (bga84, 8mmx12.5mmx1.0mm body, 0.8mm ball pitch) v dd dq14 dq12 dq6 a b c d e f g h j k l m n p r nc v ssq v ddq v ssq v ssq dq1 cke ba0 a10 v ss udm dq11 v ddq dq15 dq13 v ssq dq10 ldqs dq2 udqs v ssq v ddq v ssq clk 123 789 a3 a7 a12 dq4 nc dq9 v dd v ddq v ddl v ss v dd nc v ssq v ref v ddq v ss ldm v ddq ba1 a1 a5 a9 nc dq3 v ss we udqs dq8 v ddq ras cas a2 a6 a11 nc cs a0 a4 a8 nc clk v ssq ldqs v ddq dq7 dq5 v dd v ddq v dd v ss v ddq dq0 v ssq v ssdl odt v ssq
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 4/64 pin description pin name function pin name function a0~a12, ba0,ba1 address inputs - row address a0~a12 - column address a0~a9 a10/ap : auto precharge ba0, ba1 : bank selects (4 banks) dm (ldm, udm) dm is an input mask signal for write data. ldm is dm for dq0~dq7 and udm is dm for dq8~dq15. dq0~dq15 data-in/data-out clk, clk differential clock input ras command input cke clock enable cas command input cs chip select we command input v ddq supply voltage for dq v ss ground v ssq ground for dq v dd power v ref reference voltage dqs, dqs (ldqs, ldqs udqs, udqs ) bi-directional differential data strobe. ldqs and ldqs are dqs for dq0~dq7; udqs and ldqs are dqs for dq8~dq15. v ddl supply voltage for dll odt on-die-termination. odt is only applied to dq0~dq15, dm, dqs and dqs . v ssdl ground for dll nc no connection absolute maximum rating parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 2.3 v voltage on v dd supply relative to v ss v dd -1.0 ~ 2.3 v voltage on v ddl supply relative to v ss v ddl -0.5 ~ 2.3 v voltage on v ddq supply relative to v ss v ddq -0.5 ~ 2.3 v storage temperature t stg -55 ~ +100 c ( note * ) stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above t hose indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect reliability. note * : storage temperature is the case surface te mperature on the center /top side of the dram.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 5/64 operation temperature condition parameter symbol value unit operation temperature t c 0 ~ +95 c note: 1. operating temperature is the case surf ace temperature on the cent er/top side of the dram. 2. supporting 0 to +8 5 with full ac and dc specifications. supporting 0 to + 85 and being able to extend to + 95 with doubling auto-refresh commands in frequency to a 32ms period ( t refi = 3.9 s ) and higher temperature self-refre sh entry via a7 ?1? on emrs(2). dc operation condition & specifications dc operation condition (recommended dc operating conditions) parameter symbol min. typ. max. unit note supply voltage v dd 1.7 1.8 1.9 v 4,9 supply voltage for dll v ddl 1.7 1.8 1.9 v 4,9 supply voltage for output v ddq 1.7 1.8 1.9 v 4,9 input reference voltage v ref 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v 1,2,9 termination voltage (system) v tt v ref - 0.04 v ref v ref + 0.04 v 3,9 input logic high voltage v ih (dc) v ref + 0.125 - v ddq + 0.3 v input logic low voltage v il (dc) -0.3 - v ref - 0.125 v (all voltages referenced to vss) parameter symbol value unit note minimum required output pull-up under ac test load v oh v tt + 0.603 v 8 maximum required output pull-down under ac test load v ol v tt - 0.603 v 8 input leakage current |i li | 5 ua 5 output leakage current |i lo | 5 ua 6 output minimum source dc current ( v ddq (min); v out =1.42v ) i oh -13.4 ma 7, 8 output minimum sink dc current ( v ddq (min); v out = 0.28v ) i ol +13.4 ma 7, 8 note: 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed 2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. v ddq and v ddl track v dd . ac parameters are measured with v dd , v ddq and v ddl tied together. 5. any input 0v v in v dd ; all other balls not under test = 0v. 6. 0v v out v ddq ; dq and odt disabled. 7. the dc value of v ref applied to the receiving device is expected to be set to v tt . 8. after ocd calibration to 18 ? at t c = 25 , v dd = v ddq = 1.8v 9. there is no specific device v dd supply voltage requirement for sstl_18 comp liance. however, under all conditions v ddq must be less than or equal to v dd.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 6/64 dc specifications (idd values are for the operation range of voltage and temperature) version parameter symbol test condition -1.3 -1.5 -1.8 -2.5 unit operating current (active - precharge) idd0 one bank; t ck = t ck (idd), t rc = t rc (idd), t ras = t ras (idd)min; cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching 130 100 80 75 ma operating current (active - read - precharge) idd1 one bank; i out = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck (idd), t rc = t rc (idd), t ras = t ras (idd)min, t rcd = t rcd (idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w 160 130 100 95 ma precharge power-down standby current idd2p all banks idle; t ck = t ck (idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating 18 15 12 12 ma precharge quiet standby current idd2q all banks idle; t ck = t ck (idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating 80 60 40 40 ma idle standby current idd2n all banks idle; t ck = t ck (idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching 65 55 45 45 ma fast pdn exit mrs(12) = 0 55 45 35 35 active power-down standby current idd3p all banks open; t ck = t ck (idd); cke is low; other control and address bus inputs are stable; data bus input are floating slow pdn exit mrs(12) = 1 40 30 20 20 ma active standby current idd3n all banks open; t ck = t ck (idd), t ras = t ras (idd)max, t rp = t rp (idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching 80 60 50 50 ma operation current (read) idd4r all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (idd), al = 0; t ck = t ck (idd), t ras = t ras (idd)max, t rp = t rp (idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is the same as idd4w; 200 180 160 140 ma operation current (write) idd4w all banks open, continuous burst writes; bl = 4, cl = cl (idd), al = 0; t ck = t ck (idd), t ras = t ras (idd)max, t rp = t rp (idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching 190 170 150 130 ma
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 7/64 version parameter symbol test condition -1.3 -1.5 -1.8 -2.5 unit auto refresh current idd5 t ck = t ck (idd); refresh command every t rfc (idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching 140 120 100 100 ma self refresh current idd6 self refresh mode; clk and clk at 0v; cke ? note: 1. idd specifications are tested afte r the device is properly initialized. 2. input slew rate is sp ecified by ac input test condition. 3. idd parameters ar e specified with odt disabled. 4. data bus consists of dq, dm, dqs and dqs , idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd: low is defined as v in ? v il (ac) (max.). high is defined as v in v ih (ac) (min.). stable is defined as i nputs stable at a high or low level. floating is defined as inputs at v ref = v ddq /2 switching is defined as: address and control signal inputs are changed between high and low every other clock cycle (once per two clocks), an d dq (not including mask or strobe) signal i nputs are changed between high and low ev ery other data transfer (once per clock). 6. when t c R + 85 , idd6 must be derated by 80%. idd6 will increase by this amount if t c R + 85 and double refresh option is still enabled. 7. ac timing for idd test conditions for purposes of idd testing, the following parameters are to be utilized. -1.3 -1.5 -1.8 -2.5 parameter ddr2-1500 (7-10-10) ddr2-1333 (7-9-9) ddr2-1066 (7-7-7) ddr2-800 (5-5-5) unit cl (idd) 7 7 7 5 t ck trcd (idd) 13.3 13. 5 13.125 12.5 ns trc (idd) 80 58.12 5 58.125 57.5 ns trrd (idd) 12 10 10 10 ns tck (idd) 1.333 1. 5 1.875 2.5 ns tras (idd) min. 60 45 45 45 ns tras (idd) max. 70000 ns trp (idd) 13.3 13. 5 13.25 12.5 ns trfc (idd) 150 130 105 105 ns
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 8/64 ac operation conditions & timing specification ac operation conditions -1.3/ 1.5/ 1.8/ 2.5 parameter symbol min. max. unit note input high (logic 1) voltage v ih (ac) v ref + 0.2 v input low (logic 0) voltage v il (ac) v ref - 0.2 v input differential voltage v id (ac) 0.5 v ddq +0.6 v 1 input crossing point voltage v ix (ac) 0.5 x v ddq - 0.175 0.5 x v ddq + 0.175 v 2 output crossing point voltage v ox (ac) 0.5 x v ddq - 0.125 0.5 x v ddq + 0.125 v 2 note: 1. v id (ac) specifies the input differential voltage |v tr ? v cp | required for switching, where v tr is the true input signal (such as clk,dqs) and v cp is the complementary input signal (such as clk , dqs ). the minimum value is equal to v ih (ac) ? v il (ac). 2. the typical value of v ix / v ox (ac) is expected to be about 0.5 x v ddq of the transmitting device and v ix / v ox (ac) is expected to track variations in v ddq . v ix / v ox (ac) indicates the voltage at which differential input / output signals must cross. input / output capacitance parameter symbol min. max. unit note input capacitance (a0~a12, ba0~ba1, cke, cs , ras , cas , we , odt) c in1 2 5 pf 1 input capacitance (clk, clk ) c in2 2 5 pf 1 dqs, dqs & data input/output capacitance c i / o 2 5 pf 2 input capacitance (dm) c in3 2 5 pf 2 note: 1. capacitance delta is 0.25 pf. 2. capacitance delta is 0.5 pf.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 9/64 ac overshoot / undershoot specification value parameter pin -1.3 / 1.5 / 1.8 -2.5 unit maximum peak amplitude allowed for overshoot address, cke, cs , ras , cas , we , odt, clk, clk , dq, dqs, dqs , dm 0.5 0.5 v maximum peak amplitude allowed for undershoot address, cke, cs , ras , cas , we , odt, clk, clk , dq, dqs, dqs , dm 0.5 0.5 v address, cke, cs , ras , cas , we , odt, 0.5 0.66 v-ns maximum overshoot area above v dd clk, clk , dq, dqs, dqs , dm 0.19 0.23 v-ns address, cke, cs , ras , cas , we , odt, 0.5 0.66 v-ns maximum undershoot area below v ss clk, clk , dq, dqs, dqs , dm 0.19 0.23 v-ns
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 10/64 ac operating test conditions parameter value unit note input reference voltage ( v ref ) 0.5 x v ddq v 1 input signal maximum peak swing ( v swing (max.) ) 1.0 v 1 input signal minimum slew rate 1.0 v/ns 2,3 input level v ih / v il v input timing measurement reference level v ref v output timing measurement reference level (v otr ) 0.5 x v ddq v 4 note: 1. input waveform timing is referenced to the input signal crossing through the v ih / v il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) (min.) for rising edges and the range from v ref to v il (ac)(max.) for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. 4. the v ddq of the device under test is reference.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 11/64 ac timing parameter & specifications -1.3 -1.5 parameter symbol min. max. min. max. unit note clock period cl=7 t ck (avg) 1333 3000 1500 3000 ps 13 dq output access time from clk/ clk t ac -400 +400 -350 +350 ps 10 clk high-level width t ch (avg) 0.48 0.52 0.48 0.52 t ck (avg) 13 clk low-level width t cl (avg) 0.48 0.52 0.48 0.52 t ck (avg) 13 dqs output access time from clk/ clk t dqsck -350 +350 -300 +300 ps 10 clock to first rising edge of dqs delay t dqss -0.25 +0.25 -0.25 +0.25 t ck (avg) data-in and dm setup time (to dqs) t ds (base) 200 200 ps 4 data-in and dm hold time (to dqs) t dh (base) 200 200 ps 5 dq and dm input pulse width (for each input) t dipw 0.35 0.35 t ck (avg) address and control input setup time t is (base) 125 125 ps 4 address and control input hold time t ih (base) 250 200 ps 5 control and address input pulse width t ipw 0.6 0.6 t ck (avg) dqs input high pulse width t dqsh 0.35 0.44 t ck (avg) dqs input low pulse width t dqsl 0.35 0.44 t ck (avg) dqs falling edge to clk rising setup time t dss 0.2 0.2 t ck (avg) dqs falling edge from clk rising hold time t dsh 0.2 0.2 t ck (avg) data strobe edge to output data edge t dqsq 200 250 ps data-out high-impedance window from clk/ clk t hz t ac (max.) t ac (max.) ps 10 data-out low-impedance window from clk/ clk t lz (dqs) t ac (min.) t ac (max.) t ac (min.) t ac (max.) ps 10 dq low-impedance window from clk/ clk t lz (dq) 2 x t ac (min.) t ac (max.) 2 x t ac (min.) t ac (max.) ps 10 half clock period t hp min (t cl (abs),t ch (a bs)) min (t cl (abs),t ch (a bs)) ps 6,13 dq/dqs output hold time from dqs t qh t hp -t qhs t hp -t qhs ps dq hold skew factor t qhs 300 250 ps
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 12/64 ac timing parameter & specifications - contiuned -1.3 -1.5 parameter symbol min. max. min. max. unit note active to precharge command t ras 60 70k 45 70k ns active to active command (same bank) t rc 80 58.125 ns auto refresh row cycle time t rfc 150 130 ns active to read, write delay t rcd 13.3 13.5 ns precharge command period t rp 13.3 13.5 ns active bank a to active bank b command t rrd 12 10 ns write recovery time t wr 15 15 ns write data in to read command delay t wtr 7.5 7.5 ns 19 col. address to col. address delay t ccd 4 2 t ck average periodic refresh interval ( 0 Q t c Q + 85 ) t refi 7.8 7.8 us average periodic refresh interval ( + 85 t c Q + 95 ) t refi 3.9 3.9 us write preamble t wpre 0.35 0.35 t ck (avg) write postamble t wpst 0.4 0.6 0.4 0.6 t ck (avg) dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck (avg) 11 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck (avg) 12 load mode register / extended mode register cycle time t mrd 2 5 t ck auto precharge write recovery + precharge time t dal x - x t ck 1, 20 internal read to precharge command delay t rtp 10 7.5 ns exit self refresh to read command t xsrd 200 200 t ck exit self refresh to non-read command t xsnr t rfc + 10 t rfc + 10 ns exit precharge power-down to any non-read command t xp 5 5 t ck exit active power-down to read command t xard 5 5 t ck 3 exit active power-down to read command (slow exit / low power mode) t xards 12 - al 10 - al t ck 2,3 cke minimum pulse width (high and low pulse width) t cke 5 5 t ck
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 13/64 ac timing parameter & specifications - contiuned -1.3 -1.5 parameter symbol min. max. min. max. unit note minimum time clocks remains on after cke asynchronously drops low t delay t is + t ck (avg)*2 +t ih t is + t ck (avg) +t ih ns output impedance test driver delay t oit 0 12 0 12 ns mrs command to odt update delay t mod 0 12 0 12 ns odt turn-on delay t aond 2 2 2 2 t ck odt turn-on t aon t ac (min.) t ac (max.) + 700 t ac (min.) t ac (max.) + 2575 ps 14,16 odt turn-on (power-down mode) t aonpd t ac (min.) + 2000 2 x t ck +t ac (max.) + 1000 t ac (min.) + 2000 3 x t ck +t ac (max.) + 1000 ps odt turn-off delay t aofd 5 5 2.5 2.5 t ck 15,17, 18 odt turn-off t aof t ac (min.) t ac (max.) + 600 t ac (min.) t ac (max.) + 600 ps odt turn-off (power-down mode) t aofpd t ac (min.) + 2000 2.5 x t ck +t ac (max.) + 1000 t ac (min.) + 2000 2.5 x t ck +t ac (max.) + 1000 ps odt to power-down entry latency t anpd 5 4 t ck odt power-down exit latency t axpd 10 11 t ck
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 14/64 ac timing parameter & specifications - contiuned -1.8 -2.5 parameter symbol min. max. min. max. unit note cl=7 1875 7500 - - cl=6 x x 2500 8000 cl=5 x x 2500 8000 clock period cl=4 t ck (avg) x x x x ps 13 dq output access time from clk/ clk t ac -350 +350 -400 +400 ps 10 clk high-level width t ch (avg) 0.48 0.52 0.48 0.52 t ck (avg) 13 clk low-level width t cl (avg) 0.48 0.52 0.48 0.52 t ck (avg) 13 dqs output access time from clk/ clk t dqsck -300 +300 -350 +350 ps 10 clock to first rising edge of dqs delay t dqss -0.25 +0.25 -0.25 +0.25 t ck (avg) data-in and dm setup time (to dqs) t ds (base) 0 50 ps 4 data-in and dm hold time (to dqs) t dh (base) 75 125 ps 5 dq and dm input pulse width (for each input) t dipw 0.35 0.35 t ck (avg) address and control input setup time t is (base) 125 175 ps 4 address and control input hold time t ih (base) 200 250 ps 5 control and address input pulse width t ipw 0.6 0.6 t ck (avg) dqs input high pulse width t dqsh 0.35 0.35 t ck (avg) dqs input low pulse width t dqsl 0.35 0.35 t ck (avg) dqs falling edge to clk rising setup time t dss 0.2 0.2 t ck (avg) dqs falling edge from clk rising hold time t dsh 0.2 0.2 t ck (avg) data strobe edge to output data edge t dqsq 175 200 ps data-out high-impedance window from clk/ clk t hz t ac (max.) t ac (max.) ps 10 data-out low-impedance window from clk/ clk t lz (dqs) t ac (min.) t ac (max.) t ac (min.) t ac (max.) ps 10 dq low-impedance window from clk/ clk t lz (dq) 2 x t ac (min.) t ac (max.) 2 x t ac (min.) t ac (max.) ps 10 half clock period t hp min (t cl (abs),t ch (a bs)) min (t cl (abs),t ch (a bs)) ps 6,13
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 15/64 ac timing parameter & specifications - contiuned -1.8 -2.5 parameter symbol min. max. min. max. unit note dq/dqs output hold time from dqs t qh t hp -t qhs t hp -t qhs ps dq hold skew factor t qhs 250 300 ps active to precharge command t ras 45 70k 45 70k ns active to active command (same bank) t rc 58.125 57.5 ns auto refresh row cycle time t rfc 105 105 ns active to read, write delay t rcd 13.125 12.5 ns precharge command period t rp 13.125 12.5 ns active bank a to active bank b command t rrd 10 10 ns write recovery time t wr 15 15 ns write data in to read command delay t wtr 7.5 7.5 ns 19 col. address to col. address delay t ccd 2 2 t ck average periodic refresh interval ( 0 Q t c Q + 85 ) t refi 7.8 7.8 us average periodic refresh interval ( + 85 t c Q + 95 ) t refi 3.9 3.9 us write preamble t wpre 0.35 0.35 t ck (avg) write postamble t wpst 0.4 0.6 0.4 0.6 t ck (avg) dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck (avg) 11 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck (avg) 12 load mode register / extended mode register cycle time t mrd 2 2 t ck auto precharge write recovery + precharge time t dal wr+tn rp wr+tn rp t ck 1 internal read to precharge command delay t rtp 7.5 7.5 ns exit self refresh to read command t xsrd 200 200 t ck exit self refresh to non-read command t xsnr t rfc + 10 t rfc + 10 ns exit precharge power-down to any non-read command t xp 3 2 t ck exit active power-down to read command t xard 3 2 t ck 3 exit active power-down to read command (slow exit / low power mode) t xards 10 - al 8 - al t ck 2,3 cke minimum pulse width (high and low pulse width) t cke 3 3 t ck
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 16/64 ac timing parameter & specifications - contiuned -1.8 -2.5 parameter symbol min. max. min. max. unit note minimum time clocks remains on after cke asynchronously drops low t delay t is + t ck (avg) +t ih t is + t ck (avg) +t ih ns output impedance test driver delay t oit 0 12 0 12 ns mrs command to odt update delay t mod 0 12 0 12 ns odt turn-on delay t aond 2 2 2 2 t ck odt turn-on t aon t ac (min.) t ac (max.) + 2575 t ac (min.) t ac (max.) + 700 ps 14,16 odt turn-on (power-down mode) t aonpd t ac (min.) + 2000 3 x t ck +t ac (max.) + 1000 t ac (min.) + 2000 2 x t ck +t ac (max.) + 1000 ps odt turn-off delay t aofd 2.5 2.5 2.5 2.5 t ck 15,17, 18 odt turn-off t aof t ac (min.) t ac (max.) + 600 t ac (min.) t ac (max.) + 600 ps odt turn-off (power-down mode) t aofpd t ac (min.) + 2000 2.5 x t ck +t ac (max.) + 1000 t ac (min.) + 2000 2.5 x t ck +t ac (max.) + 1000 ps odt to power-down entry latency t anpd 4 3 t ck odt power-down exit latency t axpd 11 8 t ck note: 1. t dal [nclk] = wr[nclk] + tn rp [nclk] =wr+ru{t rp [ps]/t ck (avg)[ps] } , where wr is the value programmed in the mode register set and ru status for round up. 2. al: additive latency. 3. mrs a12 bit defines which active power-down exit timing to be applied. 4. the figures of input waveform timing 1 and 2 are re ferenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. 5. the figures of input waveform timing 1 and 2 are re ferenced from the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under test. 6. t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch (abs), t cl (abs) ), where: t ch (abs) is the minimum of the act ual instantaneous clock high time; t cl (abs) is the minimum of the ac tual instantaneous clock low time;
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 17/64 7. t qhs accounts for: a. the pulse duration distortion of on-chip clock circuits, which represents how well the actual t hp at the input is transferred to the output; and b. the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other , due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers. 8. t qh = t hp - t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: a. if the system provides t hp of 825 ps into a ddr2-1066 sdram, the dram provides t qh of 575 ps minimum. b. if the system provides t hp of 900 ps into a ddr2-1066 sdram, the dram provides t qh of 650 ps minimum. 9. ru stands for round up. wr refers to the t wr parameter stored in the mrs. 10. when the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t err (6-10per) of the input clock. (output de-ratings are re lative to the sdram input clock.) for example, if the measured jitter into a ddr2- 1066 sdram has t err (6-10per)(min.) = - 202 ps and t err (6-10per)(max.) = + 223 ps, then t dqsck (min.)(derated) = t dqsck (min.) - t err (6-10per)(max.) = -300 ps ? 223 ps = -523 ps and t dqsck (max.) (derated) = t dqsck (max.) - t err (6-10per)(min.) = 300 ps + 202 ps = +502 ps. similarly, t lz (dq) for ddr2-1066 de-rates to t lz (dq)(min.)(derated) = -700 ps - 223 ps = -923 ps and t lz (dq)(max.)(derated) = 350 ps + 202 ps = +552 ps. 11. when the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t jit (per) of the input clock. (output de-ratings are rela tive to the sdram input clock.) for example, if the measured jitter into a ddr2-1066 sdram has t jit (per)(min.) = - 72 ps and t jit (per)(max.) = + 63 ps, then t rpre (min.)(derated) = t rpre (min.) + t jit (per)(min.) = 0.9 x t ck (avg) - 72 ps = + 1615.5 ps and t rpre (max.)(derated) = t rpre (max.) + t jit (per)(max.) = 1.1 x t ck (avg) + 63 ps = + 2125.5 ps. 12. when the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t jit (duty) of the input clock. (output de-ratings are rela tive to the sdram input clock.) for example, if the measured jitter into a ddr2-1066 sdram has t jit (duty)(min.) = - 72 ps and t jit (duty)(max.) = + 63 ps, then t rpst (min.)(derated) = t rpst (min.) + t jit (duty)(min.) = 0.4 x t ck (avg) - 72 ps = + 678 ps and t rpst (max.)(derated) = t rpst (max.) + t jit (duty)(max.) = 0.6 x t ck (avg) + 63 ps = + 1188 ps. 13. refer to the clock jitter table. 14. odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond . 15. odt turn off time min is when the dev ice starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . 16. when the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t err (6-10per) of the input clock. (output de-ratings are re lative to the sdram input clock.) 17. when the device is operated with input clock jitte r, this parameter needs to be derated by { - t jit (duty)(max.) - t err (6-10per)(max.) } and { - t jit (duty)(min.) - t err (6-10per)(min.) } of the actual input clo ck. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2- 1066 sdram has t err (6-10per)(min.) = - 202 ps, t err (6- 10per)(max.) = + 223 ps, t jit (duty)(min.) = - 66 ps and t jit (duty)(max.) = + 74 ps, then t aof (min.)(derated) = t aof (min.) + { - t jit (duty)(max.) - t err (6-10per)(max.) } = - 350 ps + { - 74 ps - 223 ps} = - 647 ps and t aof (max.)(derated) = t aof (max.) + { - t jit (duty)(min.) - t err (6-10per)(min.) } = 950 ps + { 66 ps + 202 ps } = + 1218 ps. 18. for t aofd of ddr2-800/1066, the 1/2 clock of t ck in the 2.5 x t ck assumes a t ch (avg), average input clock high pulse width of 0.5 relative to t ck (avg). t aof (min.) and t aof (max.) should each be derated by the same amount as t he actual amount of t ch (avg) offset present at the dra m input with respect to 0.5. for example, if an input clock has a worst case t ch (avg) of 0.48, the t aof (min.) should be derated by subtracting 0.02 x t ck (avg) from it, whereas if an input clock has a worst case t ch (avg) of 0.52, the t aof (max.) should be derated by adding 0.02 x t ck (avg) to it. therefore, we have; t aof (min.)(derated) = t ac (min.) - [0.5 - min(0.5, t ch (avg)(min.))] x t ck (avg) t aof (max.)(derated) = t ac (max.) + 0.6 + [max(0.5, t ch (avg)(max.)) - 0.5] x t ck (avg) or t aof (min.)(derated) = min(t ac (min.), t ac (min.) - [0.5 - t ch (avg)(min.)] x t ck (avg)) t aof (max.)(derated) = 0.6 + max(t ac (max.), t ac (max.) + [t ch (avg)(max.) - 0.5] x t ck (avg)), where: t ch (avg)(min.) and t ch (avg)(max.) are the minimum and maximum of t ch (avg) actually measured at the dram input balls. 19. t wtr is at lease two clocks (2 x t ck or 2 x nck) independent of operation frequency. 20. if t ck < 1.875ns, the device can not support wr ite with auto precharge function.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 18/64 odt dc electrical characteristics parameter symbol min. typ. max. unit rtt effective impedance value for 75 setting emrs(1) [a6, a2] = 0, 1 rtt1(eff) 60 75 90 rtt effective impedance value for 150 setting emrs(1) [a6, a2) = 1, 0 rtt2(eff) 120 150 180 rtt effective impedance value for 50 setting emrs(1) [a6, a2] = 1, 1 rtt3(eff) 40 50 60 deviation of vm with respect to v ddq /2 vm -6 - +6 % note: measurement defini tion for rtt(eff) : rtt(eff) is determined by separately applying v ih (ac) and v il (ac) to test pin, and then measuring current i(v ih (ac)) and i(v il (ac)) respectively. measurement definition for vm : measure voltage (vm) at test pin with no load. ocd default characteristics parameter min. typ. max. unit note output impedance 12.6 18 23.4 1 pull-up and pull-down mismatch 0 - 4 1,2,3 output slew rate 1.5 - 5 v/ns 1,4,5 note: 1. absolute specifications: the operati on range of voltage and temperature. 2. impedance measurement condition for output source dc current: v ddq = 1.7v; v out = 1,420mv; (v out - v ddq )/i oh must be less than 23.4 for values of v out between v ddq and v ddq - 280mv. impedance measurement condition for output sink dc current: v ddq = 1.7v; v out = 280mv; v out /i ol must be less than 23.4 for values of v out between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull-do wn; both are measured at same temperature and voltage. 4. slew rate measured from v il (ac) to v ih (ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or gr eater than the slew rate as measured from ac to ac.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 19/64 clock jitter [ ddr2- 1500, 1333, 1066, 800 ] -1.3 -1.5 -1.8 -2.5 parameter symbol min. max. min. max. min. max. min. max. unit note average clock period t ck (avg) 1333 3000 1500 3000 1875 7500 2500 8000 ps 1 clock period jitter t jit (per) -30 30 -50 50 -90 90 -100 100 ps 5 clock period jitter during dll locking period t jit (per,lck) -30 30 -40 40 -80 80 -80 80 ps 5 cycle to cycle period jitter t jit (cc) -80 80 -130 130 -180 180 -200 200 ps 6 cycle to cycle clock period jitter during dll locking period t jit (cc, lck) -70 70 -120 120 -160 160 -160 160 ps 6 cumulative error across 2 cycles t err (2per) -50 50 -100 100 -132 132 -150 150 ps 7 cumulative error across 3 cycles t err (3per) -50 50 -100 100 -157 157 -175 175 ps 7 cumulative error across 4 cycles t err (4per) -50 50 -100 100 -175 175 -200 200 ps 7 cumulative error across 5 cycles t err (5per) -50 50 -100 100 -188 188 -200 200 ps 7 cumulative error across n=6,7,8,9,10 cycles t err (6-10per) -100 100 -150 150 -250 250 -300 300 ps 7 cumulative error across n=11,12,?.49,50 cycles t err (11-50per) -100 100 -150 150 -425 425 -450 450 ps 7 average high pulse width t ch (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck (avg) 2 average low pulse width t cl (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck (avg) 3 duty cycle jitter t jit (duty) -30 30 -45 45 -75 75 -100 100 ps 4 note: 1. t ck (avg) is calculated as the average clock period across any consecutive 200 cycle window. 2. t ch (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. 3. t cl (avg) is defined as the average lo w pulse width, as calculated ac ross any consecutive 200 low pulses. 4. t jit (duty) is defined as the cumulative set of t ch jitter and t cl jitter. t ch jitter is the largest deviation of any single t ch from t ch (avg). t cl jitter is the largest deviation of any single t cl from t cl (avg). t jit (duty) is not subject to production test. t jit (duty) = min./max. of { t jit (ch), t jit (cl)}, where: t jit (ch) = { t ch j - t ch (avg) where j =1 to 200} t jit (cl) = {t cl j - t cl (avg) where j =1 to 200}
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 20/64 5. t jit (per) is defined as the largest deviation of any single t ck from t ck (avg). t jit (per) = min./max. of { t ck j - t ck (avg) where j =1 to 200} t jit (per) defines the single period jitter when the dll is already locked. t jit (per, lck) uses the same defini tion for single period jitter, during the dll locking period only. t jit (per) and t jit (per, lck) are not subject to production testing. 6. t jit (cc) is defined as the difference in clock period between two consecutive clock cycles : t jit (cc) = max. of | t ck i +1 - t ck i| t jit (cc) defines the cycle to cycle jitter when the dll is already locked. t jit (cc, lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. t jit (cc) and t jit (cc, lck) are not subject to production testing. 7. t err (nper) is defined as the cumulative error across multiple consecutive cycles from t ck (avg). t err (nper) is not subject to production testing. 8. these parameters are specifie d per their average values, however it is unde rstood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (min. and max. of spec values are to be used for calculations in the table below.) parameter symbol min. max. unit absolute clock period t ck (abs) t ck (avg)(min.) + t jit (per)(min.) t ck (avg)(max.) + t jit (per)(max.) ps absolute clock high pulse width t ch (abs) t ch (avg)(min.) x t ck (avg)(min.) + t jit (duty)(min.) t ch (avg)(max.) x t ck (avg)(max.) + t jit (duty)(max.) ps absolute clock low pulse width t cl (abs) t cl (avg)(min.) x t ck (avg)(min.) + t jit (duty)(min.) t cl (avg)(max.) x t ck (avg)(max.) + t jit (duty)(max.) ps example: for ddr2-1066, t ch (abs)(min.) = (0.48 x 1875ps) - 75 ps = 825 ps input slew rate de-rating for all input signals the total t is , t ds (setup time) and t ih , t dh (hold time) required is calculated by adding the data sheet t is (base), t ds (base) and t ih (base), t dh (base) value to the t is , t ds and t ih , t dh de-rating valu e respectively. example: t ds (total setup time) = t ds (base) + t ds . setup (t is , t ds ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)(min.). setup (t is , t ds ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)(max.). if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref (dc) to ac region?, use nominal slew rate for de-rating value (see the figure of slew rate definition nominal). if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from t he ac level to dc level is used for de-rating value (see the figure of slew rate defini tion tangent). hold (t ih , t dh ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il (dc)(max.) and the first crossing of v ref (dc). hold (t ih , t dh ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih (dc)(min.) and the first crossing of v ref (dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc level to v ref (dc) region?, use nominal slew rate for de-rating va lue (see the figure of slew rate definition nominal). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual sig nal from the dc level to v ref (dc) level is used for de-rating value (see the figure of slew rate definition tangent). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih / v il (ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach v ih / v il (ac). for slew rates in between the values listed in the tables bel ow, the de-rating values may be obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 21/64 de-rating value of t ds /t dh with differential dqs(ddr2-800, 1066, 1333, 1500) dqs, dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh unit 2.0 +100 +45 +100 +45 +100 +45 - - - - - - - - - - - - ps 1.5 +67 +21 +67 +21 +67 +21 +79 +33 - - - - - - - - - - ps 1.0 0 0 0 0 0 0 +12 +12 +24 +24 - - - - - - - - ps 0.9 - - -5 -14 -5 -14 +7 -2 +19 +10 +31 +22 - - - - - - ps 0.8 - - - - -13 -31 -1 -19 +11 -7 +23 +5 +35 +17 - - - - ps 0.7 - - - - - - -10 -42 +2 -30 +14 -18 +26 -6 +38 +6 - - ps 0.6 - - - - - - - - -10 -59 +2 -47 +14 -35 +26 -23 +38 -11 ps 0.5 - - - - - - - - - - -24 -89 -12 -77 0 -65 +12 -53 ps dq slew rate (v/ns) 0.4 - - - - - - - - - - - - -52 -140 -40 -128 -28 -116 ps de-rating value of t is /t ih (ddr2-800, 1066, 1333, 1500) clk, clk differential slew rate 2.0 v/ns 1.5 v/ ns 1.0 v/ns t is t ih t is t ih t is t ih unit 4.0 +150 +94 +180 +124 +210 +154 ps 3.5 +143 +89 +173 +119 +203 +149 ps 3.0 +133 +83 +163 +113 +193 +143 ps 2.5 +120 +75 +150 +105 +180 +135 ps 2.0 +100 +45 +130 +75 +160 +105 ps 1.5 +67 +21 +97 +51 +127 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 -5 -14 +25 +16 +55 +46 ps 0.8 -13 -31 +17 -1 +47 +29 ps 0.7 -22 -54 +8 -24 +38 +6 ps 0.6 -34 -83 -4 -53 +26 -23 ps 0.5 -60 -125 -30 -95 0 -65 ps 0.4 -100 -188 -70 -158 -40 -128 ps 0.3 -168 -292 -138 -262 -108 -232 ps 0.25 -200 -375 -170 -345 -140 -315 ps 0.2 -325 -500 -295 -470 -265 -440 ps 0.15 -517 -708 -487 -678 -457 -648 ps command / address slew rate (v/ns) 0.1 -1000 -1125 -970 -1095 -940 -1065 ps
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 22/64 slew rate definition nominal
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 23/64 slew rate definition tangent
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 24/64 command truth table command note 7 cke(n-1) note 7 cke(n) cs ras cas we dm ba0,1 a10/ap a12~a11, a9~a0 note (extended) mode register set h h l l l l x op code 1,2 auto refresh h entry h l l l l h x x 10,12 l h h h refresh self refresh exit l h hx x x xx 6,9, 12 bank active h h l l h h x v row address auto precharge disable l read auto precharge enable h h l h l h x v h column address (a9~a0) 1,3 auto precharge disable l write auto precharge enable h h l h l l x v h column address (a9~a0) 1,3,17 bank selection v l precharge all banks h h l l h l x x h x hx x x entry h l l h h h x 4,11, 12,15 hx x x active power-down exit l h l h h h x x 4,8, 12,15 hx x x entry h l l h h h x 4,11, 12,15 hx x x precharge power-down exit l h l h h h x x 4,8, 12,15 dm h h x v x 16 device deselect h x h x x x x x no operation h x l h h h x x (op code = operand code, v = valid, x = don?t care, h = logic high, l = logic low) note: 1. ba during a mrs/emrs command selects which mode register is programmed. 2. mrs/emrs can be issued only at all bank precharge state. 3. burst reads or writes at bl = 4 cannot be terminated or interrupted. 4. the power-down mode does not perform any refresh operations . the duration of power-down is limited by the refresh requirements. need one clock delay to entry and exit mode. 5. the state of odt does not affe ct the states described in this table. the odt function is not available during self refresh. 6. self refresh exit is asynchronous. 7. cke (n) is the logic state of cke at clock edge n; cke (n?1) was the stat e of cke at the previous clock edge. 8. all states not shown are illegal or reserved unle ss explicitly described elsewhere in this document. 9. on self refresh, exit deselect or nop commands mu st be issued on every clock edge occurring during the t xsnr period. read commands may be issued only after t xsrd is satisfied. 10. self refresh mode can only be ent ered from all banks idle state. 11. power-down and self refresh can not be entered while read or write operations, mrs/ emrs operations or precharge operations are in progress. 12. minimum cke high / low time is t cke (min). 13. the state of odt does not affe ct the states described in this table. the odt function is not available during self refresh. 14. cke must be maintained high while the device is in ocd calibration mode. 15. odt must be driven high or low in po wer-down if the odt function is enabled. 16. used to mask write data, provided coincident with the corresponding data. 17. if t ck < 1.875ns, the device can not support wr ite with auto precharge function.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 25/64 power on and initialization ddr2 sdram must be powered up and initialized in a predefined manner. operational procedur es other than those specified may result in undefined operation. power-up and initialization sequence the following sequence is required for power-up and initialization. 1. apply power and attempt to maintain cke below 0.2 x v ddq and odt (* 1 ) at a low state (all other inputs may be undefined). - v dd (* 2 ) , v ddl (* 2 ) and v ddq are driven from a single power converter output, and - v tt is limited to 0.95v max, and - v ref tracks v ddq /2. or - apply v dd (* 2 ) before or at the same time as v ddl . - apply v ddl (* 2 ) before or at the same time as v ddq . - apply v ddq before or at the same time as v tt and v ref . at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. for the minimum of 200us after stable power and clock (clk, clk ), then apply nop or deselect and take cke high. 4. waiting minimum of 400ns then issue precharge commands fo r all banks of the device. nop or deselect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs(2) co mmand, provide ?low? to ba0, ?high? to ba1.) 6. issue emrs(3) command. (to issue emrs(3 ) command, provide ?high? to ba0 and ba1.) 7. issue emrs(1) to enable dll. (to issue "dll enable" command, provide "low" to a0, "high" to ba0 and "low" to ba1.) 8. issue a mode register set command for ?dll reset? (* 3 ). (to issue dll reset command, pr ovide ?high? to a8 and ?low? to ba0-1) 9. issue precharge commands fo r all banks of the device. 10. issue 2 or more auto refresh commands. 11. issue a mode register set command with low to a8 to initializ e device operation. (to program operation parameters without resetting the dll.) 12. at least 200 clocks after step 8, execute ocd calibration (off chip driver impedance adjustment). if ocd calibration is not used, emrs(1) ocd default comm and (a9=a8= a7=1) followed by emrs(1) ocd calibration mode exit command (a9=a8=a7=0) must be issued with other operating parameters of emrs(1). 13. the ddr2 sdram is now ready for normal operation. note : *1) to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin. *2) if dc voltage level of v ddl or v dd is intentionally changed during normal operati on, (for example, for the purpose of v dd corner test, or power saving) ?dll reset? must be executed. *3) every ?dll enable? command resets dll. therefore sequenc e 8 can be skipped during power up. instead of it, the additional 200 cycles of clock input is required to lock the dll after enabling dll. initialization sequence after power-up clk clk command 400ns pall t rp emrs(2) 200 cycle (min.) nop emrs(3) emrs(1) mrs pall ref mrs emrs(1) any command emrs(1) t mrd t mrd t mrd t mrd t rp t rfc t rfc follow ocd flow chart t oit precharge all dll enable dll reset ocd default ocd calibration mode exit ref t mrd t is t cl t ch cke
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 26/64 mode register definition mode register set [mrs] the mode register stores the data fo r controlling the various operating modes of ddr2 sdram. it programs cas latency, burst length, burst type, test mode, dll reset, wr and various vendor specific options to ma ke the device useful for variety of diffe rent applications. the default value of the mode r egister is not defined, therefore the mode register mu st be written after power-up for proper operation. the m ode register is writt en by asserting low on cs , ras , cas , we , ba0 and ba1 (the device should be in all bank precharge with cke already high prior to writing in to the mode register). the stat e of address pins a0~a12 in th e same cycle as cs , ras , cas , we , ba0 and ba1 going low are written in the mode register. the t mrd time is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operati on as long as all banks are in the idle state. the mode register is divided into various fields depending on functiona lity. the burst length is defined by a0 ~ a2. burst address seque nce type is defined by a3, cas latency (read latency from column address) is defined by a4 ~ a6. the ddr2 doesn?t support half cloc k latency mode. a7 is used for test mode. a8 is used for dll rese t. a7 must be set to low for normal mrs operation. write recover y time wr is defined by a9 ~ a11. refer to the table for specific codes. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus 0 0 pd wr dll tm cas latency bt burst length mode register note: 1. wr(min.) (write recovery for au to precharge) is determined by t ck (max.) and wr(max.) is determined by t ck (min.) wr in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up a non-integer value to the next integer ( wr[cycles] = t wr (ns)/ t ck (ns)). the mode register must be programmed to this value. this is also used with t rp to determine t dal . 2. if t ck < 1.875ns, the device can not support write with auto precharge function. wr must be set a11~a9 to 000. a3 burst type 0 sequential 1 interleave a7 mode 0 no 1 yes active power down exit timing a12 pd 0 fast exit (normal) 1 slow exit (low power) a2 a1 a0 burst length 0 0 0 reserved 0 0 1 reserved 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved a8 dll reset 0 no 1 yes ba1 ba0 mode register 0 0 mrs 0 1 emrs(1) 1 0 emrs(2) 1 1 emrs(3) : reserved cas latency a6 a5 a4 latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 write recovery for auto precharge a11 a10 a9 wr (cycles) *1 0 0 0 reserved *2 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 ddr2-800 ddr2-1066
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 27/64 burst address ordering for burst length burst length starting column address (a2, a1,a0) sequential mode interleave mode 000 0, 1, 2, 3 0, 1, 2, 3 001 1, 2, 3, 0 1, 0, 3, 2 010 2, 3, 0, 1 2, 3, 0, 1 4 011 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 8 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 mode register set 01 234 5678 command t ck precharge all banks mode register set any command t rp *2 *1 clk clk t mrd *1 : mrs can be issued only at all banks precharge state. *2 : minimum t rp is required to issue mrs command. dll enable / disable the dll must be enabled for normal operation. dll enable is requi red during power-up initialization, and upon returning to norm al operation after having the dll disabled for the purpose of debug or evaluation (upon ex iting self refresh mode, the dll is enabled automatically). any time the dll is enabled, 200 cl ock cycles must occur before a read command can be issued. output drive strength the normal drive strength for all outputs is specified to be sstl_18. the device also supports a weak drive strength option, intended for lighter load and/or point-to-point environments.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 28/64 extended mode register set-1 [emrs(1)] the emrs(1) stores the data for enabling or disabling dll, output driver strength, additi ve latency, odt, disable dqs , ocd program. the default value of the emrs(1) is not defined, therefore emrs(1) must be written after power up for proper operation . the emrs(1) is written by asserting low on cs , ras , cas , we , ba1 and high on ba0 (the device should be in all bank precharge with cke already high prior to writing into emrs(1 )). the state of address pins a0~a12 in the same cycle as cs , ras , cas , we and ba1 going low and ba0 going high are written in the emrs(1). the t mrd time is required to complete the wr ite operation to the emrs(1). the emrs(1 ) contents can be changed using the same command and clock cycle requirements during normal operation as lo ng as all banks are in the idle state. a0 is used for dll enable or disable. a1 is used for reducing output driver strength. the additive lat ency is defined by a3~a5. a7~a9 are used for ocd control. a10 is used for dqs disable. odt setting is defined by a2 and a6. in single ended mode, the dqs signals are internally disabled and don?t care. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 qoff 0 *1 dqs ocd program rtt additive latency rtt ods dll a10 dqs enable 0 enable 1 disable note: 1. a11 is reserved for future use and must be set to 0. 2. when adjustable mode of driver impedance is issued, the previously set value of al must be applied. 3. after setting to default state of driv er impedance, ocd calibration mode needs to be exited by setting a9~a7 to 000. 4. output disabled - dqs, dqss, dqs s. this feature is used in conjuncti on with dimm idd measurements when iddq is not desired to be included. a0 dll enable 0 enable 1 disable a6 a2 rtt (nominal) 0 0 disable 0 1 75 1 0 150 1 1 50 a1 output driver strength control 0 normal (100%) 1 weak (60%) a12 qoff *4 0 output buffer enable 1 output buffer disable additive latency a5 a4 a3 latency 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 reversed ba1 ba0 mode register 0 0 mrs 0 1 emrs(1) 1 0 emrs(2) 1 1 emrs(3): reserved driver impedance adjustment a9 a8 a7 ocd operation 0 0 0 ocd calibration mode exit 0 0 1 drive-1 0 1 0 drive-0 1 0 0 adjustable mode *2 1 1 1 ocd default state *3
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 29/64 extended mode register set-2 [emrs(2)] the emrs(2) stores the data for enabling or disabling high temper ature self refresh rate. the def ault value of the emrs(2) is n ot defined, therefore emrs(2) must be written after power up for proper operation. the emrs(2) is written by asserting low on cs , ras , cas , we , ba0 and high on ba1 (the device should be in all bank precharge with cke already high prior to writing into emrs(2)). the state of address pins a0~a12 in the same cycle as cs , ras , cas , we and ba0 going low and ba1 going high are written in the emrs(2). the t mrd time is required to complete the wr ite operation to the emrs(2). the emrs(2 ) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. a7 is used for high temperature self refresh rate enable or disable. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 0 0 *1 srf 0 *1 dcc *2 pasr *3 *note: 1. a0~a2, a4~a6 and a8~a12 are reserved for future use and must be set to 0. 2. user may enable or disable the dcc (duty cycle corrector) by programming a3 bit accordingly. 3. if pasr (partial array self refresh) is enabled, data located in areas of th e array beyond the specified address range will be lost if self refresh is entered. data integrity will be maintained if t ref conditions are met and no self refresh command is issued. if the pasr feature is not supported, emrs(2)[a0-a2] must be set to 000 when programming emrs(2). ba1 ba0 mode register 0 0 mrs 0 1 emrs(1) 1 0 emrs(2) 1 1 emrs(3): reserved a7 high temperature self refresh rate 0 disable 1 enable a3 dcc enable 0 disable 1 enable a2 a1 a0 partial array self refresh 0 0 0 full array 0 0 1 half array (ba[1:0]=00&01) 0 1 0 quarter array (ba[1:0]=00) 0 1 1 not defined 1 0 0 3/4 array (ba[1:0]=01, 10&11) 1 0 1 half array (ba[1:0]=10&11) 1 1 0 quarter array (ba[1:0]=11) 1 1 1 not defined
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 30/64 extended mode register set-3 [emrs(3)] ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 0 note: emrs(3) is reserved for future. all bits except ba0 and ba1 are reserved for fu ture use and must be set to 0 when setting to mode register during initialization. ba1 ba0 mode register 0 0 mrs 0 1 emrs(1) 1 0 emrs(2) 1 1 emrs(3): reserved
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 31/64 off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature. every calibrati on mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be se t before entering ocd impedance adjustment and odt (on die termination) should be carefully contro lled depending on system environment. ocd flow chart start emrs(1) : driver-1 dq & dqs high ; dqs low mrs should be set before entering ocd impedance adjustment and odt should be carefully controlled depending on system environment test emrs(1) : ocd calibration mode exit emrs(1) : enter adjustable mode bl=4 code input to all dqs inc, dec, or nop emrs(1) : ocd calibration mode exit emrs(1) : ocd calibration mode exit all ok need calibration emrs(1) : driver-0 dq & dqs low ; dqs high test emrs(1) : ocd calibration mode exit emrs(1) : enter adjustable mode bl=4 code input to all dqs inc, dec, or nop emrs(1) : ocd calibration mode exit need calibration emrs(1) : ocd calibration mode exit all ok end
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 32/64 emrs(1) for ocd impedance adjustment ocd impedance adjustment can be done using the followi ng emrs(1) mode. in drive mode, a ll outputs are driven out by ddr2 sdram. in drive-1mode, all dq, dqs signals are driven high and all dqs signals are driven low. in drive-0 mode, all dq, dqs signals are driven low and all dqs signals are driven high. in adjustable mo de, bl = 4 of operation code data must be used. in case of ocd default stat e, output driver characteristics have a nominal impedance value of 18 ? during nominal temperature and voltage conditions. output dr iver characteristics for ocd default stat e are specified in o cd default characteri stics table. ocd applies only to normal full strength output drive setting defined by emrs(1) and if weak strength is set or adjustab le mode is used, ocd default out put driver characteristics are not applicable. after ocd calibration is completed or driver streng th is set to default, subsequent emrs(1) commands not intended to adjust ocd characteristics must specify a9-a7 as '000' in order to maintain the default or calibrated value. driver impedance adjustment mode a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 device-1: dq,dqs high and dqs low 0 1 0 device-0: dq,dqs low and dqs high 1 0 0 adjustable mode 1 1 1 ocd default state adjust ocd impedance to adjust output driver impedance, controll ers must issue emrs(1) command for adjustable mode along with a 4bit burst code to ddr2 sdram as in the following table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive th is burst code to all dqs at the same time . dt0 in the following table means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output impedance is adjusted for all dqs simultaneously and after oc d calibration, all dqs of a given device will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further incr ement or decrement code has no effect. the default setting may be any step within the 16 step range. when adjustable mode co mmand is issued, al from previously set value must be applied. ocd adjustment table dt0 dt1 dt2 dt3 pull-up driver strength pull-down driver strength 0 0 0 0 nop nop 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by 1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by 1 step 0 1 1 0 decrease by 1 step increase by 1 step 1 0 0 1 increase by 1 step decrease by 1 step 1 0 1 0 decrease by 1 step decrease by 1 step others reserve reserve
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 33/64 ocd adjustable mode clk clk emrs(1) emrs(1) nop nop dt0 t ds t dh dt1 dt2 dt3 command dqs, dqs dq ocd adjustable ocd calibration m ode e x it t wr wl dm note: for proper operation of adjustable mode, wl = rl - 1 = al + cl - 1 clocks and t ds / t dh should be met as the above timing diagram. for input data pattern for adjustment, dt0 - dt3 is a fixed order and "not affected by mrs addressing mode (ie. sequential or interleave). ocd driver mode clk clk emrs(1) emrs(1) nop t oit command dqs, dqs dq enter drive mode ocd calibration mode exit high-z dqs high and dqs low for drive-1, dqs low and dqs high for drive-0 high-z dqs low for drive-0 dqs high for drive-1 t oit note: drive mode, both drive-1 and drive-0, is used for controllers to me asure ddr2 sdram driver impedance. in this mode, all output s are driven out t oit after ?enter drive mode? co mmand and all output drivers are turned-off t oit after ?ocd calibration mode exit? command as the above timing diagram.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 34/64 odt (on die termination) on die termination (odt) is a feature t hat allows a ddr2 sdram to turn on/o ff termination resistance for each dq, all dqs/ dqs , and all dm signals via the odt control pin. the odt featur e is designed to improve sig nal integrity of the memory channel by allowing the dram controller to independently tu rn on/off termination resistance for any or all devices. the odt function is supported for active and standby modes. odt is turned off and not supported in self refresh mode. timing for odt update delay clk clk emrs(1) t aofd command odt internal rtt setting t is nop t mod(min.) t mod(max.) old setting updating new setting note: t aofd must be met before issuing emrs(1) command. odt must remain low for t he entire duration of t mod window. odt timing for active and standby mode clk clk cke odt internal te rm r e s . t0 t1 t2 t3 t4 t5 t6 t aofd t is t aond t is t aon(min.) t aon(max.) t aof(min.) t aof(max.) rtt
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 35/64 odt timing for power-down mode clk clk cke odt internal te rm r e s . t0 t1 t2 t3 t4 t5 t6 t is t is t aonpd(min.) t aonpd(max.) t aofpd(min.) rtt t aofpd(max.)
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 36/64 odt timing mode switch at entering power-down mode cke clk clk t-5 t-4 t - 3 t-2 t-1 t0 t1 t2 t3 t is t anpd entering slow exit active power-down mode or precharge power-down mode. active and standby mode timings to be applied. odt internal te r m r e s . t is t aofd rtt power-down mode timings to be applied. odt internal te r m r e s . t is rtt active and standby mode timings to be applied. odt internal te rm r e s . t is rtt power-down mode timings to be applied. odt internal te r m r e s . t is rtt t aofpd(max.) t aond t aonpd(max.)
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 37/64 odt timing mode switch at exiting power-down mode cke clk clk t0 t1 t4 t5 t6 t7 t8 t9 t10 t11 t is t axpd exiting from slow active power-down mode or precharge power-down mode. active and standby mode timings to be applied. odt internal te r m r e s . t is t aofd rtt power-down mode timings to be applied. odt internal term re s. t is rtt active and standby mode timings to be applied. odt internal term re s. t is rtt power-down mode timings to be applied. odt internal te rm r e s . t is rtt t aofpd(max.) t aond t aonpd(max.)
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 38/64 precharge the precharge command is used to precharge or close a b ank that has activated. the command is issued when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank select addresses (ba0, ba1) and a10 are used to define which bank is precharged when the command is in itiated. for write cycle, t wr (min.) must be satisfied until the precharge command can be issued. after t rp from the precharge, a bank active command to the same bank can be initiated. bank selection for precharge by address bits a10/ap ba1 ba0 precharge 0 0 0 bank a only 0 1 0 bank b only 0 0 1 bank c only 0 1 1 bank d only 1 x x all banks nop & device deselect the device should be deselected by deactivating the cs signal. in this mode, ddr2 sdram would ignore all the control inputs. the ddr2 sdram are put in nop mode when cs is active and by deactivating ras , cas and we . for both deselect and nop, the device should finish the current operation when this command is issued. bank active the bank active command is issued by holding cas and we high with cs and ras low at the rising edge of the clock (clk). the ddr2 sdram has four independent banks, so two bank select addresses ( ba0, ba1) are required. the bank active command to the first read or write command must meet or exceed the minimum of ras to cas delay time (t rcd (min.)). once a bank has been activated, it must be pr echarged before another bank active comma nd can be applied to the same bank. the minimum time interval between interleaved bank active command (bank a to bank b and vice versa) is the bank to bank delay time (t rrd min). bank active command cycle clk clk act t ccd t0 t1 t2 t3 tn tn+1 tn+2 tn+3 command posted read act posted read pre act bank a row addr. bank b address bank b row addr. bank b col. addr. bank a row addr. additive latency (al) t rcd=1 t rrd bank a col. addr. t ras t rc pre bank a t rp bank a active bank b active bank a precharge bank b precharge bank a active bank a read begins
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 39/64 read bank this command is used after the bank active command to init iate the burst read of data. the read command is initiated by activating cs , cas , and deasserting we at the same clock sampling (rising) edge as described in the command truth table. the length of the burst and the cas latency time will be determined by the values programmed during the mrs command. write bank this command is used after the bank active command to initiate the burst write of data. the write command is initiated by activating cs , cas , and we at the same clock sampling (rising) edge as de scribe in the command trut h table. the length of the burst will be determined by the val ues programmed during the mrs command. posted cas posted cas operation is supported to make command and data bus e fficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a read or write command to be issued immedi ately after the bank active command (or any time during the t rrd period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the cas latency (cl). therefore if a user chooses to issue a r/w command before the t rcd (min), then al (greater than 0) must be written into the emrs(1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read latenc y is defined as the sum of additive latency plus cas latency (rl=al+cl). read or write operations using al allow seamless bursts. read followed by a write to the same bank < al= 2; cl= 3 ; bl = 4> -1 03456 7 89 10 11 12 cmd 12 clk clk active bank a dout0 dout1 dout2 dout3 din0 din1 din2 din3 wl = rl -1 =4 al = 2 cl = 3 >= t rcd rl = al + cl = 5 dqs/dqs dq read bank a write bank a < al= 0; cl= 3; bl = 4 > -1 0 34 5 6 7 8 9 10 11 12 cmd 12 clk clk write bank a dout0 dout1 dout2 dout3 din0 din1 din2 din3 wl = rl -1 = 2 al = 0 cl = 3 >= t rcd rl = al + cl = 3 dqs/dqs dq active bank a read bank a
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 40/64 essential functionality for ddr2 sdram burst read operation the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column addr ess for the burst. the delay from the start of the command to when the data from the first cell appears on t he outputs is equal to the value of the read latency (rl). the dqs is driven low 1 clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of dqs. each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mrs and the al is defined by the emrs(1). read (data output) timing clk clk dout0 t ch dqs t dqsq(max.) t cl dqs dq dout1 dout2 dout3 t qh t rpst t qh t dqsq(max.) t rpre burst read < rl= 5 (al= 2; cl= 3); bl= 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd posted cas read a nop al = 2 t8 nop nop nop nop nop nop nop dqs,dqs cl = 3 rl = 5 douta0 douta1 douta2 douta3 dqs =< t dqsck < rl= 3 (al= 0; cl= 3); bl= 8 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd nop t8 nop nop nop nop nop nop nop dqs,dqs cl = 3 rl = 3 douta4 douta5 douta6 douta7 read a dqs douta0 douta1 douta2 douta3 =< t dqsck
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 41/64 burst read followed by burst write < rl= 5; wl= (rl-1) = 4; bl= 4 > clk clk t0 t1 tn-1 tn tn+1 tn+2 tn+3 tn+4 cmd posted cas read a nop tn+5 nop nop nop nop nop nop dqs,dqs wl = rl-1 = 4 rl = 5 douta0 douta1 douta2 douta3 dqs posted cas write a t rtw (read to write-turn around-time) dina0 dina1 dina2 dina3 note: the minimum time from the burst read command to the burst write command is defined by a read to write-turn around-time(t rtw ), which is 4 clocks in case of bl = 4 operation, 6 clocks in case of bl = 8 operation (8 clocks in case of bl = 4 operation, 16 clo cks in case of bl = 8 operation for speed grade -1.3). seamless burst read < rl= 5; al= 2; cl= 3; bl = 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd posted cas read a al = 2 t8 nop nop nop nop nop nop nop dqs,dqs cl = 3 rl = 5 douta0 douta1 douta2 douta3 dqs posted cas read b doutb0 doutb1 doutb2 note: the seamless burst read operation is supported by enabling a read command at every other clock for bl = 4 operation, and every 4 clock for bl = 8 operation. this operation is allo wed regardless of same or different banks as long as the banks are activated.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 42/64 burst write operation the burst write command is issued by having cs , cas and we low while holding ras high at the rising edge of the clock (clk). the address inputs determine the starting column addre ss. write latency (wl) is defi ned by a read latency (rl) min us one and is equal to (al + cl -1); and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first dqs strobe. a data strobe signal (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at t he first rising edge of the dqs following the preamble. the t dqss specification must be satisfied fo r each positive dqs transition to it s associated clock edge during write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed, which is 4 or 8 bit burst. when the burst has finished, any additional data suppl ied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completi on of the burst write to bank pr echarge is the write recovery time (t wr ). write (data input) timing dqs dqs dq t ds t wpre din0 din1 din2 din3 t ds dm t dh t dh dqs dqs t dqsh t dqsl t wpst burst write < rl= 5 (al= 2; cl= 3); wl= 4; bl= 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd posted cas write a nop wl=rl-1=4 tn nop nop nop nop nop precharge nop dqs,dqs dina0 dina1 dina2 dina3 dqs case1 : with t dqss(max) t dss wl=rl-1=4 dqs,dqs dina0 dina1 dina2 dina3 dqs t dsh case2 : with t dqss(min) t dqss t dqss >= t wr >= t wr < rl= 3 (al= 0; cl= 3); wl= 2; bl= 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd nop tn nop nop nop nop bank a active nop write a wl=rl-1=2 dqs,dqs dina0 dina1 dina2 dina3 dqs t dqss t wr precharge >= t rp
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 43/64 burst write followed by burst read < rl= 5 (al= 2; cl= 3); wl= 4; bl= 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd nop wl=rl-1=4 t8 nop nop nop nop nop dqs,dqs dina0 dina1 dina2 dina3 dq writetoread=cl-1+bl/2+t wtr >=t wtr cl = 3 t9 nop nop nop dqs dqs al = 2 douta0 posted cas read a rl = 5 note: the minimum number of clock from the burst write command to the burst read command is [cl - 1 + bl/2 + t wtr ]. this t wtr is not a write recovery time (wr) but the time required to transfer the 4 bit write data from the input buffer into sense amplifiers in the array. seamless burst write < rl= 5; wl= 4; bl= 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd t8 nop nop nop nop nop nop nop dqs,dqs wl = rl-1 = 4 dqs dina0 posted cas write a posted cas write b dina1 dina2 dina3 dinb0 dinb1 dinb2 dinb3 note: the seamless burst write operation is supported by enabling a write comm and at every other clock for bl = 4 operation, and every 4 clock for bl = 8 operation. this operation is allo wed regardless of same or different banks as long as the banks are activated.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 44/64 read interrupted by a read burst read can only be interrupted by another read with 4 bit burst boundary. any other case of read interrupt is not allowed. < cl= 3; al= 0; rl= 3; bl= 8 > clk clk cmd nop nop nop nop nop nop dqs,dqs dqs a0 read a read b nop a1 a3 a2 b0 b3 b2 b1 b4 b7 b6 b5 nop note: 1. read burst interrupt function is only allo wed on burst of 8. burst inte rrupt of 4 is prohibited. 2. read burst of 8 can only be interrupted by another read command. read burst interruption by write command or precharge command is prohibited. 3. read burst interrupt must occur exactly tw o clocks after previous read command. any other read burst interrupt timings are prohibited. 4. read burst interruption is allowed to any bank inside dram. 5. read burst with auto precharge enabled is not allowed to interrupt. 6. read burst interruption is allowed by another read with auto precharge command. 7. all command timings are referenced to burst l ength set in the mode register. they are not referenced to actual burst. for example, minimum read to prec harge timing is al + bl/2 where bl is the burst length set in the mrs and not the actual burst (which is shorter because of interrupt).
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 45/64 write interrupted by a write burst wirte can only be interrupted by another write with 4 bit bur st boundary. any other case of write interrupt is not allowe d. < cl= 3; al= 0; rl= 3; wl= 2; bl= 8 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd t8 write a nop nop nop nop nop dqs,dqs dqs a0 nop nop nop a1 a3 a2 b0 b3 b2 b1 b4 b7 b6 b5 write b note: 1. write burst interrupt function is only allo wed on burst of 8. burst inte rrupt of 4 is prohibited. 2. write burst of 8 can onl y be interrupted by another write comm and. write burst interruption by read command or precharge command is prohibited. 3. write burst interrupt must occur exactly two clocks after previous write co mmand. any other write burst interrupt timings are prohibited. 4. write burst interruption is allowed to any bank inside dram. 5. write burst with auto precharge enabled is not allowed to interrupt. 6. write burst interruption is allowe d by another write with auto precharge command. 7. all command timings are referenced to burst l ength set in the mrs. they are not referenced to actual burst. for example, minimum write to precharge timing is wl+bl/2+ t wr where t wr starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 46/64 burst read followed by precharge minimum read to precharge command spacing to the same bank = al + bl/2 + max(t rtp , 2) - 2 clocks. for the earliest possible precharge, the pr echarge command may be issued on the rising edg e which is ?additive latency (al) + bl/2 clocks? after a read command. a new bank active command may be issued to the same bank after the precharge time (t rp ). a precharge command cannot be issued until t ras is satisfied. the minimum read to precharge spacing has also to satisfy a mi nimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a read to precharge command. this time is called t rtp (read to precharge). for bl = 4, this is the time from the actual read (al after the read command) to precharge command. fo r bl = 8, this is the time from al + 2 clocks after the rea d to the precharge command. < rl= 4 (al= 1; cl= 3) > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd posted cas read a nop al + bl/2 clks t8 nop nop nop nop precharge bank a active dqs,dqs douta0 dqs >= t rp nop al = 1 cl = 3 rl = 4 douta1 douta2 douta3 >= t ras cl = 3 >= t rtp cmd posted cas read a nop al + bl/2 clks nop nop nop nop precharge a dqs,dqs douta0 dqs nop al = 1 cl = 3 rl = 4 douta1 douta2 douta3 douta4 douta5 douta6 douta7 >= t rtp nop bl = 8 bl = 4 < rl= 5 (al= 2; cl= 3); bl= 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd posted cas read a nop al + bl/2 clks t8 nop nop nop nop precharge a bank a active dqs,dqs douta0 dqs >= t rp nop al = 2 cl = 3 rl = 5 douta1 douta2 douta3 >= t ras cl = 3 >= t rtp < rl= 6 (al= 2; cl= 4); bl= 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd posted cas read a nop al + bl/2 clks t8 nop nop nop nop precharge a bank a active dqs,dqs douta0 dqs >= t rp nop al = 2 cl = 4 rl = 6 douta1 douta2 douta3 >= t ras cl = 4 >= t rtp
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 47/64 < rl= 4 (al= 0; cl= 4); bl=8 > clk clk cmd nop nop nop nop precharg a bank a active nop dqs,dqs al+2 clks + max(t rtp ;2) dqs posted cas write a t0 t1 t2 t3 t4 t5 t6 t7 t8 nop >=t rp cl = 4 al = 0 >= t ras douta0 douta1 douta2 douta3 douta4 douta5 douta6 douta7 rl = 4 burst write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 clocks + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can b e issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay. < wl= (rl-1) = 3; bl=4> clk clk cmd nop nop nop nop precharg a nop dqs,dqs dqs posted cas write a t0 t1 t2 t3 t4 t5 t6 t7 t8 nop >=t wr wl = 3 dina0 nop dina1 dina2 dina3 < wl= (rl-1) = 4; bl=4 > clk clk cmd nop nop nop nop precharg a nop dqs,dqs dqs posted cas write a t0 t1 t2 t3 t4 t5 t6 t7 t9 nop >=t wr wl = 4 dina0 nop dina1 dina2 dina3
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 48/64 write data mask by dm one write data mask (dm) pin for each 8 data bits (dq) will be supported on ddr2 sdram, consist ent with the implementation on ddr2 sdram. it has identical timings on write operations as the data bits, and t hough used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. dm is not used during read cycles. data mask timing dqs dqs t1 t2 t3 t4 t5 tn dq dm din din din din din din din din din write mask iatency = 0 example: < wl= 3; al= 0; bl= 4 > clk clk t0 t1 t2 t3 t4 t5 t6 t7 command wl t8 dqs,dqs din0 dq t wr nop writ t dqss din2 dm [t dqss(min.) ] wl dqs,dqs din0 dq t dqss din2 dm [t dqss(max.) ]
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 49/64 read with auto precharge if a10 is high when a read command is issued, the read with auto precharge function is engaged. the device starts an auto precharge operation on the rising edge which is (al + bl /2) cycles later than the read with ap command if t ras (min) and t rtp (min) are satisfied. if t ras (min) is not satisfied at the edge, the start point of auto precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the start point of auto precharge operation will be delayed until t rtp (min) is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4, the minimum ti me from read_ap to the next bank active command becomes al + (t rtp + t rp )*. for bl = 8, the time from read_ap to the next bank active command is al + 2 + (t rtp + t rp )*. (note: ?*? means ?rouded up to the next integer?). < rl= 4 (al= 1; cl= 3) > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd t8 nop nop nop nop nop bank a active nop dqs,dqs dqs posted cas read a nop al+bl/2 clks >=t rp autoprecharge cl = 3 al = 1 >= t rtp douta0 douta1 douta2 douta3 douta4 douta5 douta6 douta7 rl = 4 t rtp precharge begins here bl = 8 t rtp <= 2 clocks cmd nop nop nop nop nop bank a active nop dqs,dqs dqs posted cas read a nop >=al+t rtp+ t rp autoprecharge cl = 3 al = 1 t rp douta0 douta1 douta2 douta3 rl = 4 t rtp precharge begins here bl = 4 t rtp > 2 clocks a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) the precharge time (t rp ) has been satisfied from the clock at which the auto precharge begins. (2) the ras cycle time (t rc ) from the previous bank activation has been satisfied.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 50/64 < rl= 5 (al= 2; cl= 3); bl= 4; t rcd = 3 clocks; t rtp < = 2 clocks > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd posted cas read a nop >= t ras(min) t8 nop nop nop nop bank a active dqs,dqs douta0 dqs >= t rp nop al = 2 cl = 3 rl = 5 douta1 douta2 douta3 >= t rc t rc limit nop autoprecharge autoprecharge begins clk clk cmd posted cas read a nop >= t ras(min) nop nop nop nop bank a active dqs,dqs douta0 dqs >= t rp nop al = 2 cl = 3 rl = 5 douta1 douta2 douta3 t rp limit nop autoprecharge autoprecharge begins >= t rc write with auto precharge if a10 is high when a write command is issued, the write with auto precharge function is engaged (if t ck < 1.875ns, the device can not support write with auto precharge function). the device automatically begins precharge operation after the completion o f the burst write plus write recovery time (t wr ). the bank active command undergoing auto precharge from the completion of the write burst may be reactivated if the fo llowing two conditions are satisfied. (1) the data-in to bank activate delay time (t wr + t rp ) has been satisfied. (2) the ras cycle time (t rc ) from the previous bank activation has been satisfied. < wr = 2; bl= 4; t rp = 3 clocks > clk clk t0 t1 t2 t3 t4 t5 t6 t7 cmd posted cas write a nop tm nop nop nop nop bank a active dqs,dqs dina0 dqs >= t rp nop wl = rl-1 = 2 >= t rc t rc limit nop autoprecharge auto precharge begins clk clk cmd posted cas write a nop nop nop nop nop bank a active dqs,dqs dina0 dqs nop dina1 dina2 dina3 >= t rc t wr + t rp nop autoprecharge dina1 dina2 dina3 >= t wr t0 t3 t4 t5 t6 t7 t8 t9 t12 auto precharge begins >= t rp >= t wr wl = rl-1 = 4
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 51/64 auto refresh & self refresh auto refresh an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock(clk). all banks must be precharged and idle for t rp (min) before the auto refresh command is applied. an address counter, internal to the device, supplies the bank address during the refres h cycle. no control of the ex ternal address bus is required once this cycle has started. when the refresh cy cle has completed, all banks will be in the idle state. a delay between the auto ref resh command and the next bank active command or subsequent auto refresh command must be greater than or equal to the t rfc (min).to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight refresh commands c an be posted, meaning that the ma ximum absolute interval between any refresh command and the next refresh command is 9 x t refi . command cke = high t rp pre au t o refresh cmd t rfc clk clk
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 52/64 self refresh a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock (clk). odt must be turned off before issuing self refres h command, by either driving odt pin low or using emrs(1) command. once the command is registered , cke must be held low to keep the devic e in self refresh mode. the dll is automatically disabled upon entering self refresh and is automa tically enabled upon exiting self refresh. when the device has entered self refresh mode, all of the extern al signals except cke, are ?don?t care?. for proper self refresh operation all power supply pins (v dd , v ddq , v ddl and v ref ) must be at valid levels. the device initiates a minimum of one refresh command internally within t cke period once it enters self refresh mode. the clock is internally disabled during self refresh operation to save powe r. self refresh mode must be remained t cke (min). the user may change the external clock frequ ency or halt the external clock one clock after self refresh entry is registered, however, the clock must be restarted and stable before the device can exit self re fresh operation. the procedure for exiting se lf refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high. once self refresh exit is registered, a delay of t xsrd (min) must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self refresh exit period t xsrd for proper operation except for self refresh re-entry. upon exit from self refresh, the device can be put back into self refresh mode after waiting t xsnr (min) and issuing one refresh command. nop or deselect commands must be registered on each positiv e clock edge during the self refresh exit interval t xsnr . odt should be turned off during t xsrd . the use of self refresh mode in troduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. u pon exit from self refresh, t he device requires a minimum of one extra auto refresh command before it is put back into self refresh mode. clk clk t0 t1 t2 t3 t4 t5 t6 tn cke tm odt >= t xsnr t rp command t aofd >= t xsrd t is t is t is t ih t is t ck t ch t cl note: 1. device must be in the ?all banks idle? state prior to entering self refresh mode. 2. odt must be turned off t aofd before entering self refresh mode, and can be turned on again when t xsrd timing is satisfied. 3. t xsrd is applied for a read or a read with auto precharge command. 4. t xsnr is applied for any command except a read or a read with auto precharge command.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 53/64 power-down power-down is synchronously entered when cke is registered low (no accesses can be in progress). cke is not allowed to go low while mrs or emrs command time, or read or write operation is in progress. cke is allowed to go low while any of other operations such as bank active, precharge or auto precharge, or auto refresh is in progress. the dll should be in a locked stat e when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a bank active command in any bank, this mode is refe rred to as active power-down. entering power-down deactivates the input and output buffers, excluding clk, clk , odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active power-down, but the dll is kept enabled dur ing fast exit active power-down. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the device, and odt should be in a valid state but all other inpu t signals are ?don?t care?. cke low must be maintained until t cke has been satisfied. power-down duration is limited by 9 times t refi of the device. the power-down state is synchronously exited when cke is regi stered high (along with a nop or deselect command). cke high must be main tained until t cke has been satisfied. a valid, executable command can be applied with power-down exit latency, t xp , t xard , or t xards , after cke goes high. clk clk cke command valid t is t ih t is t ih t ih t is t ih nop nop valid valid valid t cke t cke enter power-down mode t xp, t xard, t xards exit power-down mode t cke :don?tcare read to power-down entry clk clk command read cke cke should be kept high until the end of burst operation dq t0 t1 t2 tx tx+1 tx+2 tx+3 high al + cl douta0 douta1 douta2 douta3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 dqs dqs bl = 4 clk clk command read cke cke should be kept high until the end of burst operation dq t0 t1 t2 tx tx+1 tx+2 tx+3 high al + cl douta0 douta1 douta2 douta3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 dqs dqs bl = 8 douta4 douta5 douta6 douta7
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 54/64 read with auto precharge to power-down entry clk clk command read cke cke should be kept high until the end of burst operation dq t0 t1 t2 tx tx+1 tx+2 tx+3 al+bl/2 with t rtp =7.5ns and t ras(min.) satisfied al + cl douta0 douta1 douta2 douta3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 dqs dqs bl = 4 clk clk command read cke cke should be kept high until the end of burst operation dq t0 t1 t2 tx tx+1 tx+2 tx+3 al + cl douta0 douta1 douta2 douta3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 dqs dqs bl = 8 douta4 douta5 douta6 douta7 pre pre start internal precharge al+bl/2 with t rtp =7.5ns and t ras(min.) satisfied write to power-down entry clk clk command write cke dq t0 t1 tm tm+1 tm+2 tm+3 tx wl dina0 dina1 dina2 dina3 tx+1 tx+2 ty ty+1 ty+2 ty+3 dqs dqs bl = 4 clk clk command write cke dq t0 t1 tm tm+1 tm+2 tm+3 tm+4 dina0 dina1 tm+5 tx tx+1 tx+2 tx+3 tx+4 dqs dqs bl = 8 t wtr dina2 dina3 dina4 dina5 dina6 dina7 t wtr wl
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 55/64 write with auto precharge to power-down entry clk clk command write a cke dq t0 t1 tm tm+1 tm+2 tm+3 tx wl dina0 dina1 dina2 dina3 tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 dqs dqs bl = 4 clk clk command write a cke dq t0 t1 tm tm+1 tm+2 tm+3 tm+4 dina0 dina1 tm+5 tx tx+1 tx+2 tx+3 tx+4 dqs dqs bl = 8 t wr dina2 dina3 dina4 dina5 dina6 dina7 t wr wl pre pre note: if t ck < 1.875ns, the device can not support write with auto precharge function. auto refresh/ bank active/ precharge to power-down entry clk clk command cmd cke t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 cke can go to low one clock after a command note: cmd could be auto refresh/ bank active/ precharge command. mrs/emrs to power-down entry clk clk t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 cke mrs/ emrs command t mrd
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 56/64 asynchronous cke low event ddr2 sdram requires cke to be maintained ?high? for all valid operat ions as defined in this data sheet. if cke asynchronously drops ?low? during any valid operation, the device is not guaranteed to preserve the c ontents of array. if this event occurs, memory controller must satisfy t delay before turning off the clocks. stable clocks must exist at the input of device before cke is raised ?high? again. the device must be fully re-initialized (steps 4 ~ 13) as described in initialization sequence. the device is ready for normal operation after the initialization sequence. clk clk cke t ck t delay stable clocks cke asynchronously drops low clockscanbeturnedoff af t er t his p o in t clock frequency change in precharge power-down mode ddr2 sdram input clock frequency can be changed under following condition: the device is in precharge power-down mode. odt must be turn ed off and cke must be at logic low level. a minimum of 2 clocks must be waited after cke goes low before clock frequency ma y change. the device input clock frequency is allowed to change only between t ck (min) and t ck (max). during input clock frequency change, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new clocks must be provided before precharge power-down may be exited and dll must be reset via mrs after precharge power-down exit. depending on new clock frequency an additional mrs command may need to be issued to appropriately set the wr, cl etc .. during dll re-lock period, od t must remain off. after the dll lock time, the device is ready to operate with new clock frequency. clk clk minimum 2 clocks required before changing frequency t0 t1 t2 t4 t rp tx tx+1 ty ty+1 ty+2 ty+3 ty+4 tz cke odt nop command nop nop nop dll reset nop vaild t aofd tx p 200 clocks frequency change occurs here stable new clock bef o re p o wer d o wn exi t odt is off during dll reset
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 57/64 functional truth table *7 current state cs ras cas we address command action h x x x x desel nop or power-down l h h h x nop nop or power-down l h l x ba, ca, a10 read / reada / write / writea illegal (*1) l l h h ba, ra active bank active, latch ra l l h l ba, a10 / a10 pre / prea precharge / precharge all l l l h x refresh refresh (*2) idle l l l l op-code mode-add mrs / emrs mode register setting / extended mode register setting (*2) h x x x x desel nop l h h h x nop nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto precharge l l h h ba, ra active illegal (*1) l l h l ba, a10 /a10 pre / prea precharge / precharge all l l l h x refresh illegal bank active l l l l op-code mode-add mrs / emrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto precharge (*1, 4) l h l l ba, ca, a10 write / writea illegal (*1) l l h h ba, ra active illegal (*1) l l h l ba, a10 / a10 pre / prea illegal (*1) / illegal l l l h x refresh illegal read l l l l op-code mode-add mrs / emrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h l h ba, ca, a10 read / reada illegal (*1) l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin new write, determine auto-precharge (*1, 4) l l h h ba, ra active illegal (*1) l l h l ba, a10 / a10 pre / prea illegal (*1) / illegal l l l h x refresh illegal write l l l l op-code mode-add mrs / emrs illegal
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 58/64 current state cs ras cas we address command action h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h l h ba, ca, a10 read / reada illegal (*1) l h l l ba, ca, a10 write / writea illegal (*1) l l h h ba, ra active illegal (*1) l l h l ba, a10 / a10 pre / prea illegal (*1) / illegal l l l h x refresh illegal read with auto precharge l l l l op-code mode-add mrs / emrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h l h ba, ca, a10 read / reada illegal (*1) l h l l ba, ca, a10 write / writea illegal (*1) l l h h ba, ra active illegal (*1) l l h l ba, a10 pre / prea illegal (*1) / illegal l l l h x refresh illegal write with auto precharge l l l l op-code mode-add mrs / emrs illegal h x x x x desel nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h l x ba, ca, a10 read / reada / write / writea illegal (*1) l l h h ba, ra active illegal (*1) l l h l ba, a10 / a10 pre / prea nop (idle after t rp ) l l l h x refresh illegal pre-chargin g l l l l op-code mode-add mrs / emrs illegal h x x x x desel nop (bank active after t rcd ) l h h h x nop nop (bank active after t rcd ) l h l x ba, ca, a10 read / reada / write / writea illegal (*1, 5) l l h h ba, ra active illegal (*1) l l h l ba, a10 / a10 pre / prea illegal l l l h x refresh illegal row activating l l l l op-code mode-add mrs / emrs illegal
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 59/64 current state cs ras cas we address command action h x x x x desel nop (bank active after t wr ) l h h h x nop nop (bank active after t wr ) l h l h ba, ca, a10 read / reada illegal (*1, 6) l h l l ba, ca, a10 write / writea write / writea l l h h ba, ra active illegal (*1) l l h l ba, a10 / a10 pre / prea illegal (*1) / illegal l l l h x refresh illegal write recovering l l l l op-code mode-add mrs / emrs illegal h x x x x desel nop (bank active after t wr ) l h h h x nop nop (bank active after t wr ) l h l x ba, ca, a10 read / reada / write / writea illegal (*1) l l h h ba, ra active illegal (*1) l l h l ba, a10 / a10 pre / prea illegal (*1) / illegal l l l h x refresh illegal write recovering with auto precharge l l l l op-code mode-add mrs / emrs illegal h x x x x desel nop (idle after t rfc ) l h h h x nop nop (idle after t rfc ) l h l x ba, ca, a10 read / reada / write / writea illegal l l h h ba, ra active illegal l l h l ba, a10 / a10 pre / prea illegal l l l h x refresh illegal refresh l l l l op-code mode-add mrs / emrs illegal h x x x x desel nop (idle after t mrd ) l h h h x nop nop (idle after t mrd ) l h l x ba, ca, a10 read / reada / write / writea illegal l l h h ba, ra active illegal l l h l ba, a10 / a10 pre / prea illegal l l l h x refresh illegal (extended) mode register setting l l l l op-code mode-add mrs / emrs illegal h = high level, l = low level, x = don?t care ba = bank address, ra =row address, ca = column address, nop = no operation illegal = device operation and / or data integrity ar e not guaranteed. note: 1. this command may be issued for other bank s, depending on the state of the banks. 2. all banks must be in ?idle?. 3. all ac timing specs must be met. 4. only allowed at the boundary of 4 bits burst. burst interruption at other timings is illegal. 5. available in case t rcd is satisfied by al setting. 6. available in case t wtr is satisfied. 7. if t ck < 1.875ns, the device can not support wr ite with auto precharge function.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 60/64 simplified states diagram power-up and initialization sequence ocd calibration settign mrs emrs self refreshing idle all banks precharged refreshing precharge power- down srf ref ckeh ckel activating (e)mrs pr bank active active power -down ckeh ckel ckel ckel ckel ckel ckel reading write write read reading with auto precharge writing with auto precharge precharging write write read rda rda rda wra wra wra pr, pra pr, pra pr, pra read ckeh act automatic sequence command sequence ckel = cke low ckeh = cke high act = activate wr(a) = write (with auto precharge) rd(a) = read (with auto precharge) pr(a) = precharge (all) (e)mrs = (extended) mode register set srf = enter self refresh ref = auto refresh
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 61/64 packing dimensions 84-ball ddrii sdram ( 8x12.5x1.2 mm ) symbol dimension in mm dimension in inch min norm max min norm max a 1.20 0.047 a 1 0.25 0.30 0.40 0.010 0.012 0.016 b 0.37 0.45 0.50 0.015 0.018 0.020 d 7.90 8.00 8.10 0.311 0.315 0.319 e 12.40 12.50 12.60 0.488 0.492 0.496 d 1 6.40 bsc 0.252 bsc e 1 11.20 bsc 0.441 bsc e 0.80 bsc 0.031 bsc controlling dimension : millimeter.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 62/64 packing dimensions 84-ball ddrii sdram ( 8x12.5x1.0 mm ) symbol dimension in mm dimension in inch min norm max min norm max a 1.00 0.039 a 1 0.25 0.30 0.40 0.010 0.012 0.016 b 0.37 0.45 0.50 0.015 0.018 0.020 d 7.90 8.00 8.10 0.311 0.315 0.319 e 12.40 12.50 12.60 0.488 0.492 0.496 d 1 6.40 bsc 0.252 bsc e 1 11.20 bsc 0.441 bsc e 0.80 bsc 0.031 bsc controlling dimension : millimeter.
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 63/64 revision history revision date description 0.1 2013.03.11 original 0.2 2013.06.26 1. modify the specification of i dd 2. add a note for t wtr 0.3 2013.09.10 1. delete speed grade -3 2. correct the figure of ac input test signal waveforms 1.0 2013.10.17 1. delete "preliminary" 2. modify input / output capacitance 1.1 2013.12.12 1. add a description into emrs (1) 2. correct the specification of tck (max) 3. delete tfaw 1.2 2014.01.17 add speed grade -1.5 1.3 2014.03.20 modify the voltage for speed grade -1.5 1.4 2014.05.30 1. add speed grade -1.3 2. modify wr setting of mrs for speed grade -1.5
esmt m14d5121632a (2k) elite semiconductor memory technology inc. publication date : may 2014 revision : 1.4 64/64 important notice all rights reserved. no part of this document may be reproduc ed or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the product s or specification in this document without notice. the information contained herein is presen ted only as a guide or examples for the application of our products. no res ponsibility is assumed by esmt for any infringement of patents, copyrights, or ot her intellectual propert y rights of third parties which may result from its use. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inhere ntly a certain rate of failure. to minimize risks associated with custom er's application, adeq uate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or caus e physical injury or property damage. if products described here are to be used for such kinds of applicat ion, purchaser must do its own quality assurance test ing appropriate to such applications.

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